1. Technical Field
The present invention relates to a reference voltage circuit for generating a reference voltage.
2. Description of the Related Art
Description is given of a conventional reference voltage circuit. FIG. 7 is a circuit diagram illustrating the conventional reference voltage circuit.
In a metal oxide semiconductor (MOS) transistor that operates in weak inversion, when a gate width is represented by W; a gate length, L; a threshold voltage, Vth; a gate-source voltage, Vgs; the electron charge quantity, q; the Boltzmann's constant, k; absolute temperature, T; and constants each determined depending on a process, Id0 and n, a drain current Id is calculated using Expression (61).Id=Id0·(W/L)·exp{(Vgs−Vth)·q/nkT}  (61)
When a thermal voltage is expressed by “nkT/q” and is represented by UT, Expression (62) is established.Id=Id0·(W/L)·exp{(Vgs−Vth)/UT}  (62)
Accordingly, the gate-source voltage Vgs is calculated using Expression (63).Vgs=UT·ln [Id/{Id0·(W/L)}]+Vth  (63)
P-type MOS (PMOS) transistors 43 to 45 have a current mirror connection, and hence drain currents Id41, Id42, and Id45 of the PMOS transistors 43, 44, and 45 take the same value.
A voltage generated across a resistor 58 is a voltage (Vgs41−Vgs42) determined by subtracting the gate-source voltage Vgs42 of an N-type MOS (NMOS) transistor 42 that operates in weak inversion from the gate-source voltage Vgs41 of an NMOS transistor 41 that operates in weak inversion. Accordingly, based on the voltage (Vgs41−Vgs42) and a resistance R58 of the resistor 58, the drain current Id42 is calculated, and the drain current Id45 is also calculated. Then, Expression (64) is established.Id45=Id42=(Vgs41−Vgs42)/R58  (64)
Accordingly, when a resistance of a resistor 59 is represented by R59, an output voltage Vref generated across the resistor 59 is calculated using Expression (65).Vref=R59·Id45=(R59/R58)·(Vgs41−Vgs42)  (65)
Through Expression (63), when a gate width of the NMOS transistor 41 is represented by W41; a gate length of the NMOS transistor 41, L41; a threshold voltage of the NMOS transistor 41, Vth41; a gate width of the NMOS transistor 42, W42; a gate length of the NMOS transistor 42, L42; a threshold voltage of the NMOS transistor 42, Vth42; and a difference between the threshold voltages of the NMOS transistors 41 and 42, ΔVth (ΔVth=Vth41−Vth42), the output voltage Vref is calculated using Expression (66).Vref=(R59/R58)·[UT·ln {(W42/L42)/(W41/L41)}+ΔVth]  (66)
As expressed in Expression (66), each aspect ratio of the NMOS transistors 41 and 42 is adjusted so that a temperature characteristic of the first term and a temperature characteristic of the second term may cancel each other. As a result, the output voltage Vref becomes less likely to be dependent on temperature (see, for example, JP 3024645 B).
However, it is between a source and a back gate of the NMOS transistor 42 and a ground terminal 100 that the resistor 58 exists. Accordingly, process fluctuations in the resistor 58 cause fluctuations in the threshold voltage Vth42 as well. In other words, the threshold voltage Vth42 depends not only on process fluctuations in the NMOS transistor 42 but also on the process fluctuations in the resistor 58. As a result, a reference voltage, which should be independent of temperature, is determined based on the difference between the threshold voltages of the NMOS transistors 41 and 42 (ΔVth=Vth41−Vth42), resulting in a problem of an unstable reference voltage.